文章引用情况
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Accelerating the evolution of a systolic array-based evolvable hardware system2
High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications3
The ANTAREX domain specific language for high performance computing4
FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems5
Autonomous power management in mobile devices using dynamic frequency scaling and reinforcement learning for energy minimization6
Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems7
Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures8
Near-memory computing: Past, present, and future9
Non linearity mitigation and dispersion reduction using Bussgang theorem, modified MSE and improved MLE equalizers10
Lightweight chaotic image encryption algorithm for real-time embedded system: Implementation and analysis on 32-bit microcontroller